Release notes

Version 1.1 - Dec. 13, 2023

Add pwrOnRst port to CbtLane
- CbtLane has single reset input so far despite using several clock signals. Logics driven by clkPar and logics driven by clkIndep and clkIdelayRef should not be reset by the same reset signal. To fix this, another reset signal, pwrOnRst, is introduced; it is expected that this reset is generated by the PLL lock signal, which generates clkIndep and clkIdelayRef signals.

High-precision mode of MIKUMARI pulse
- The MIKUMARI pulse function newly supports the high-precision mode. This mode can transmit the 4-bit extra data together with the pulse, i.e., the 3-bit pulse type and the 4-bit data are simultaneously transferred. The existing pulse transmission mode is called the low-latency mode.
CBT serdesOffset and firstBitPatt ports
- The serdesOffset and firstBitPatt ports are added to the CbtLane. The serdesOffset port provides the relative phase between the input bit pattern and the ClkPar signal. This port is for the Local Area Common Clock Protocol (LACCP).
- The firstBitPatt port provides the bit pattern before starting the bit-slip process. This port is for debug.
Support CDCM-8-2.5
- CDCM-8-2.5 was tested with Kintex-7 FPGA with thr reference clock signal frequency of 125 MHz. MMCM was used for the clock signal recovery.
Disable the clock monitor function
- The clock monitor function in the CBT was disabled.

Enable again the clock monitor function
- It was found that the clock monitor function is essential to deterministically set the IDELAY tap value in the initialization process.
Slightly modify the CDCM-RX initialization process.